This invention relates to the field of microelectronics and semiconductor device packaging and, more particularly to multilayer thin film wiring structures having alternating layers of vias and custom wiring planes or other features such as capture pads, engineering change pads, etc.
In the field of microelectronic fabrication for computer applications, there is an ever increasing demand for faster components. The semiconductor devices, themselves, are being continuously upgraded to increase speed. However, it is estimated that one-half of the processing time is taken up in interconnection and power distribution circuitry. The delays encountered in the electronic package are therefore as critical to the overall performance time as are the device speeds.
The typical electronic package for high performance applications consists of a multilayer ceramic (MLC) substrate having semiconductor devices mounted on the top surface. The bottom surface of the substrate typically contains I/0 pins for connection to a card or board. It is well known that the processing delay inherent in the package can be significantly reduced by the use of thin film wiring structures on top of the MLC substrate.
Various techniques have been proposed for making these thin film wiring structures. What they all seem to have in common is that the conductive metallization is deposited a layer at a time. That is, a first layer containing a via is formed then a second layer containing a wiring line or capture pad in electrical contact with the via is formed. Such a layer by layer process raises severe continuity, reliability and yield concerns. Most importantly, the greatest disadvantage of the layer by layer process is the large number of processing steps which are necessary to lay down even a single thin film wiring layer. Indeed, the task of forming multilayer structures containing one or more thin film wiring layers by the layer by layer process is a formidable one.
Beyer et al. U.S. Pat. No. 4,944,836, the disclosure of which is incorporated by reference herein, is an example of the layer by layer process. In FIG. 4, a 3 layer structure is formed. Each layer is formed by depositing a dielectric layer, patterning a trench and then filling the trench with conductive material. The conductive material may be deposited by sputtering, chemical vapor deposition or electroplating. Thereafter, the layer is planarized by chemical-mechanical polishing techniques. The structure is now ready for the second layer to be formed.
A similar process is demonstrated in Shaw et al., "Photosensitive Glass For Producing Recessed Metallurgy, Eliminating Need For Planarization", IBM Technical Disclosure Bulletin, Vol. 26, No. 3A, p. 1094 (August 1983), the disclosure of which is incorporated by reference herein. This reference discloses the use of a photosensitive glass to form the pattern.
In Park, et al. U.S. patent application Ser. No. 399,058, filed Aug. 28, 1989, the disclosure of which is incorporated by reference herein, the single-layer pattern is formed in a photosensitive polyimide. Metal is deposited by suitable techniques (for example, vacuum deposition, electroplating, etc.) in the pattern and on the polyimide. The excess metal is removed by a machining-type planarization technique.
Leary-Renick U.S. Pat. No. 4,622,058, the disclosure of which is incorporated by reference herein, discloses another layer by layer process wherein each single layer comprises a glass which is then fired. The pattern, in this case step-shouldered vias, can be formed by ablating the glass. Thereafter, metal is deposited in the vias.
Chow et al. U.S. Pat. No. 4,789,648, the disclosure of which is incorporated by reference herein, discloses the formation of a dual via-wiring channel on a semiconductor device. This structure is formed by first depositing first and second insulation layers, for example quartz, and then etching a via in the first layer and a wiring channel in the second layer. The multilayered structure is metallized by a conformal metallization technique and then chem-mech polished.
Fan U.S. Pat. No. 4,572,764 and Williston U.S. Pat. 4,631,111, the disclosures of which are incorporated by reference herein, illustrate the formation of a multilayer structure using two layers of photosensitive polymeric material. In Fan, the two layers of polymeric material are imagewise exposed and developed separately while in Williston the two layers are imagewise exposed and developed simultaneously. In any event, the patterns so formed are then selectively metallized by electrolessly plating. A subsequent material removal process is not required since the pattern is not plated up to fill the depth of the pattern.
Notwithstanding the past efforts of those concerned with multilayered thin film structures, there still remains a need for an improved process for making such structures. This improved process should be characterized by reduced complexity and higher yields.
Accordingly, it is an object of the present invention to have an improved process for making multilayered thin film structures.
This and other objects of the invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.